Forum Discussion
Altera_Forum
Honored Contributor
Honored Contributorhow to implement a VHDL testbench for verilog module?
I have a verilog project,and already run and got my .vo file,now someone else want to write a VHDL testbench for my project to implement a whole scheduling emulation,how? ie: my verilog module nam...
Altera_ForumHonored Contributor
Honored Contributorin ModelSim-Altera Edition I can't use a VHDL testbench for a verilog vo file?what about SE edition?
