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Altera_Forum's avatar
Altera_Forum
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13 years ago

How to handle this hold time violated?

I have a design, part of the design is :

PLL_6us_3us_300ns pll1(.areset(~ireset),.inclk0(clk),.c0(clk_6us),.c1(clk_3us),.c2(clk_300ns),.locked(lock));

always @(negedge clk)

begin

if ((counterScan>14 && counterScan<31) || (counterSystemReset>300 && counterSystemReset<321) )

CK_Scan<=clk_300ns;

else

CK_Scan<=1'b0;

end

I have a PLL module, the "clk" period is 40ns, and pll will generate clock signals whose period are 6us, 3us, and 300ns respectively.

Then I will create a gated clock signal "CK_Scan", when the "counterScan" or "counterSystemReset" in a specific range, the CK_Scan will be 300ns clock signal.

In order to avoid a glitch, I made the "CK_Scan" as a register output, and use the quick clock "clk" to drive this it, but I use the negedge to trigger it.

After I did the STA in TimeQuest, there is a hold violated as attachment. I can't understand this since it assign "clk_300ns" and "clk" as launch and latch clock respectively. instead I think both launch and latch clock should be "clk".

In my .sdc file, the commands I have as following:

create_clock -name sys_clk -period 40.0 [get_ports clk]

derive_pll_clocks

derive_clock_uncertainty

Is that my judgment right? If it is, why TimeQuest mistake it? If I am wrong, anbody can help me understand this and how can I handle this violated?

Thanks very much!

16 Replies

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  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    I suggest you use one clock only, without PLL then create various rates equivaalent to your required PLL outputs. Use the one clock with a chosen enable and you are in Altera's safe hands.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    --- Quote Start ---

    if clk_scan is detected as clock then it means you are triggering some other assignments on its edge. You better avoid that though this is not where the hold time is reported.

    If clk_300 rising pulse is always in phase with clk then clk_300 is synchronously related to clk and I wouldn't do edge swap.

    --- Quote End ---

    Yes, I found I used CK_Scan to trigger a module inside FPGA and now I changed it to clk_300ns. So you mean I should use positive edge of "clk"? I didn't understand this since clk_300ns will change exactly in the positive edge of clk, before clk posedge, clk_300ns maybe "0" and after posedge it became "1", why does this not cause metastable&#65311;

    And without PLL, how can I create the different rate clocks?

    Thanks very much for your time!
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    --- Quote Start ---

    Yes, I found I used CK_Scan to trigger a module inside FPGA and now I changed it to clk_300ns. So you mean I should use positive edge of "clk"? I didn't understand this since clk_300ns will change exactly in the positive edge of clk, before clk posedge, clk_300ns maybe "0" and after posedge it became "1", why does this not cause metastable&#65311;

    --- Quote End ---

    aligned edges are in our favor just like the case of synchronous registers driven by same clock. Q output is always behind edge by tCO of register so don't worry.

    --- Quote Start ---

    And without PLL, how can I create the different rate clocks?

    Thanks very much for your time!

    --- Quote End ---

    use counter(s) to divide the clk rate into whatever patterns you want < clk rate. for example a counter that runs from 0 to 99 then you toggle a signal everytime it is halfway through at count 49 or set output to 1 at some specific counts and 0 otherwise.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    --- Quote Start ---

    aligned edges are in our favor just like the case of synchronous registers driven by same clock. Q output is always behind edge by tCO of register so don't worry.

    use counter(s) to divide the clk rate into whatever patterns you want < clk rate. for example a counter that runs from 0 to 99 then you toggle a signal everytime it is halfway through at count 49 or set output to 1 at some specific counts and 0 otherwise.

    --- Quote End ---

    Yes, I originally use counter to create clock signals. But the staffs in Altera suggests me using PLL if the PLL can generate the clock we want. Since the clock signals generate from PLL is more accurate than counter. But yes, in this case, the counter should be feasible since my clock rates are slow.

    I think the hold time violated may be caused by some other reasons, I will try to figure it out.

    Thanks so much!
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    --- Quote Start ---

    Yes, I originally use counter to create clock signals. But the staffs in Altera suggests me using PLL if the PLL can generate the clock we want. Since the clock signals generate from PLL is more accurate than counter. But yes, in this case, the counter should be feasible since my clock rates are slow.

    --- Quote End ---

    Don't listen to them!!

    --- Quote Start ---

    I think the hold time violated may be caused by some other reasons, I will try to figure it out.

    --- Quote End ---

    Well it is reported on clk_scan register. Notice here that your clk_scan register is unlikely to be io register. If you want clk_scan to have less jitter then you better end it up nicely at io register before sending it out.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    --- Quote Start ---

    Don't listen to them!!

    Well it is reported on clk_scan register. Notice here that your clk_scan register is unlikely to be io register. If you want clk_scan to have less jitter then you better end it up nicely at io register before sending it out.

    --- Quote End ---

    Hi kaz, but counter actually can not generate very accurate clock. I try that, for example use counter to create a slow clock (40ns *256), the TimeQuest will tell me the real clock period, which is not exactly 10240ns. If you need very accurate clock, counter does not work very well.

    Yes, Clk_Scan is not outputted directly, it connects to a mux, the output of mux will be output to the chip. I will check what I can modify.

    Thanks very much!