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Yes, I originally use counter to create clock signals. But the staffs in Altera suggests me using PLL if the PLL can generate the clock we want. Since the clock signals generate from PLL is more accurate than counter. But yes, in this case, the counter should be feasible since my clock rates are slow.
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Don't listen to them!!
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I think the hold time violated may be caused by some other reasons, I will try to figure it out.
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Well it is reported on clk_scan register. Notice here that your clk_scan register is unlikely to be io register. If you want clk_scan to have less jitter then you better end it up nicely at io register before sending it out.
Honored Contributor
