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Yes, I found I used CK_Scan to trigger a module inside FPGA and now I changed it to clk_300ns. So you mean I should use positive edge of "clk"? I didn't understand this since clk_300ns will change exactly in the positive edge of clk, before clk posedge, clk_300ns maybe "0" and after posedge it became "1", why does this not cause metastable？
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aligned edges are in our favor just like the case of synchronous registers driven by same clock. Q output is always behind edge by tCO of register so don't worry.
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And without PLL, how can I create the different rate clocks?
Thanks very much for your time!
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use counter(s) to divide the clk rate into whatever patterns you want < clk rate. for example a counter that runs from 0 to 99 then you toggle a signal everytime it is halfway through at count 49 or set output to 1 at some specific counts and 0 otherwise.
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