--- Quote Start ---
aligned edges are in our favor just like the case of synchronous registers driven by same clock. Q output is always behind edge by tCO of register so don't worry.
use counter(s) to divide the clk rate into whatever patterns you want < clk rate. for example a counter that runs from 0 to 99 then you toggle a signal everytime it is halfway through at count 49 or set output to 1 at some specific counts and 0 otherwise.
--- Quote End ---
Yes, I originally use counter to create clock signals. But the staffs in Altera suggests me using PLL if the PLL can generate the clock we want. Since the clock signals generate from PLL is more accurate than counter. But yes, in this case, the counter should be feasible since my clock rates are slow.
I think the hold time violated may be caused by some other reasons, I will try to figure it out.
Thanks so much!
Honored Contributor
