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if clk_scan is detected as clock then it means you are triggering some other assignments on its edge. You better avoid that though this is not where the hold time is reported.
If clk_300 rising pulse is always in phase with clk then clk_300 is synchronously related to clk and I wouldn't do edge swap.
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Yes, I found I used CK_Scan to trigger a module inside FPGA and now I changed it to clk_300ns. So you mean I should use positive edge of "clk"? I didn't understand this since clk_300ns will change exactly in the positive edge of clk, before clk posedge, clk_300ns maybe "0" and after posedge it became "1", why does this not cause metastable？
And without PLL, how can I create the different rate clocks?
Thanks very much for your time!
Honored Contributor
