Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

How to handle the Hold time is violated?

In my design, after analysis in TimeQuest, there are 4 paths that hold time are violated, the slack time is negative. What is normal approach to handle the case that hold time is violated?

Thanks very much.

9 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    Do you have the Fitter option to "Optimize Hold Timing" for "All Paths" turned on? If so, then you may need to over-constrain the failing Hold paths with a set_min_delay constraint.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    --- Quote Start ---

    Do you have the Fitter option to "Optimize Hold Timing" for "All Paths" turned on? If so, then you may need to over-constrain the failing Hold paths with a set_min_delay constraint.

    --- Quote End ---

    Hi, when I firstly compiled, I already had the Fitter option to "Optimize Hold Timing" for "All Paths" turned on. But after I read your post, I realized that my hold time violated is only happening in Fast 0C mode, so I turn on another Fitter option is "Optimize multi-corner timing". Then after I fully complied it again, the hold violated disappear. Should I use that option?

    Thanks.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    Yes, I should have mentioned that. That option should always be on. I'm not even sure why it is an option.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    --- Quote Start ---

    Yes, I should have mentioned that. That option should always be on. I'm not even sure why it is an option.

    --- Quote End ---

    Thanks. In this case, I am lucky that Quartus II help me to remove the hold violated. If both two options be enabled, but the violated still there, could you take a simple example to explain how I can use set_min_delay constraint to remove violated?

    Hope this will not cost too much time.

    Thanks very much again.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    Sorry, just got back from 2 week's vacation today. If you haven't figured this out yet, try this (assuming your Hold Relationship is 0):

    set_min_delay 0.200 -from <source node> -to <destination node>.

    If this isn't enough, you can try increasing the amount from 200 ps to a larger number.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    all those fitter options may help you in timing closure if you need to get the design generated asap. but in the long run, if you still encounter the timing violation too often, you need to revisit your design.

    firstly, constraint the paths properly. the nets which are supposed to be multicycle (doesn't need to reach the destination by 1 clk cycle) and false paths should be specified, to ease up the fitter process.

    ultimately, read and apply some design for performance techniques. reduce fanouts by using duplicated registers, apply pipelining. this will get rid of your timing issue once and for all.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    --- Quote Start ---

    all those fitter options may help you in timing closure if you need to get the design generated asap. but in the long run, if you still encounter the timing violation too often, you need to revisit your design.

    firstly, constraint the paths properly. the nets which are supposed to be multicycle (doesn't need to reach the destination by 1 clk cycle) and false paths should be specified, to ease up the fitter process.

    ultimately, read and apply some design for performance techniques. reduce fanouts by using duplicated registers, apply pipelining. this will get rid of your timing issue once and for all.

    --- Quote End ---

    Thanks so much!
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    ideally you would like to go to chip planner and place the design element by element. altera has good manual on that, named Analyzing and Optimizing the Design Floorplan with the Chip Planner.in it you can actually see where physically your module is located in which elements, connections and delays between each element, so on. never used it. iv heard that somehow timing analyzer gives you a file. you can feed that file back to fitter and fitter will take in consideration all the delays and fit to avoid the delays. never used it aswell :) hope it will guide you to the correct direction.