How to handle the Hold time is violated?

ideally you would like to go to chip planner and place the design element by element. altera has good manual on that, named Analyzing and Optimizing the Design Floorplan with the Chip Planner.in it you can actually see where physically your module is located in which elements, connections and delays between each element, so on. never used it. iv heard that somehow timing analyzer gives you a file. you can feed that file back to fitter and fitter will take in consideration all the delays and fit to avoid the delays. never used it aswell :) hope it will guide you to the correct direction.