How to handle the Hold time is violated?

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all those fitter options may help you in timing closure if you need to get the design generated asap. but in the long run, if you still encounter the timing violation too often, you need to revisit your design.

firstly, constraint the paths properly. the nets which are supposed to be multicycle (doesn't need to reach the destination by 1 clk cycle) and false paths should be specified, to ease up the fitter process.

ultimately, read and apply some design for performance techniques. reduce fanouts by using duplicated registers, apply pipelining. this will get rid of your timing issue once and for all.

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Thanks so much!