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Altera_Forum's avatar
Altera_Forum
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18 years ago

How to fix timing issues using the timing assignment options?

Hi,everybody.

I make this post for your help. I have tried hardly,but just can't solve it myself.

A description about my issue:

(my device:EP1C6Q240C8;QII:6.1;AD:ADC08200--National semiconductor)

My design is about data acquirement and storage.There are four ADs which sample clocks between them are 90 degree phase shift. Two sample clocks are generated by a single PLL with 0 and 90 degree phase shift,and another two are generated by inverting the fore two,then get 180 and 270 degree phase shift. They are 250MHz.(ADs are used overclocking,the NS says,it's no problem )

Now I can correctly receive the data acquired by there ADs,but the fouth AD's(with 270 degree sample clock) data storage have a problem. After read data from memory,make a plot in debug software,it shows some data in transition have been stored. I consider it as a setup and hold violation.What I implemented is adjusting the storage clock's dealy to satisfy data valide period and prevent the transiting data being stored.Then I use "Logic Cell Insertion"(single point assignment),but it seems no use. I have set "Ignores LCELL buffers" off and unchecked "Perform WYSIWYG primitive resynthesis". I have also tried other assigements,like "Maximum Delay""Fast Input Register"...etc.but no effect on my design. At the same time, I am not very familiar with how and when to use them.

Do anybody have experience in fixing timing issue using assignments? Or,how to adjust setup and hold violation?

If there are ambiguity expressions,please tell me. Sorry for not good at using English.

Thank you.

Best Regards.

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  • Altera_Forum's avatar
    Altera_Forum
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    18 years ago

    Thank you so much larsen and Rysc.

    Hi,Rysc.You have quite known my design.I do have to use the PLL with inverters.I also belive that 250MHz data flow can be correctly handled. It just should ensure setup and hold condition of the input registers directly associated with input I/O(external 250MHz data flow input port). I mean that four DFFs,which have a clock input of 250MHz(In the file I attached as "SinPout.zip") . After correctly handled,I can use them under 125MHz internally.

    But,there is someting boring. All the 250MHz data flow input ports are assigned in bank2,ranged from pin-197 to pin-240,however, on chip RAMs are locate from X17_Y1--X17_Y20. I need 16 blocks of 20 total.So,the route delay from data input can't be almost the same when reach RAMs.Now I still have a little problem about data storage. Is it a fatal problem when QII fits my design? I will attach a shoot screen of time closure floorplan.

    By the way,FPGAs' density are increasing.So the performance not the resource usage is most concerned . Then maybe timing constraints should give more attention.How to use assignment editor correctly and high efficiently? Expect QII handbook, are there any other ways or desig reference?

    Thank you.

    Best Regards.
  • Altera_Forum's avatar
    Altera_Forum
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    18 years ago

    I can't say for sure whether that will meet timing or not. It will probably be close. Since you have clock constraints(done when creating the PLL), Quartus will tell you very directly if it can make timing or not, so you need to implement that portion of the design and see what happens. Since you're capturing data, my guess is you could add another stage of registers between the IO registers and the memory, which adds one latency delay, but should allow you to easily meet internal timing. Usually data capture applications can handle this quite easily, although I don't know if you have latency requirements in your system.

  • Altera_Forum's avatar
    Altera_Forum
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    18 years ago

    In my opinion, timing constraints relay on your units you choose .You must know how many delay and where they occur.

    Of course ,Quartus can help you analyze your work!

    I am troubled by timing constraints too! Hope it can help you!

    Regards.
  • Altera_Forum's avatar
    Altera_Forum
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    18 years ago

    Thanks for concern ：）

    I have changed the FPGA into -6 speed grade.Now,I'm bothered by devices' distinction. The project can run well on one FPGA,but fails on the others.So,I have to adjust timing of every single device. It's indeed a hard work.

    Some of friends have also encountered this situation before,in their cases,the distinction just occurs between different batch of FPGA. Unfortunately,I'm suffering on every piece.

    Then ,when making your schemes, the distinction also should be considered.
  • Altera_Forum's avatar
    Altera_Forum
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    18 years ago

    You are right!

    I have tried different devices with one same project, the scheme shows me different devices have different initial logic ,of course the time required is different, sometimes the time slack ,Tsu and Th even can not be met.

    So, the distinction should be considered.