How to fix timing issues using the timing assignment options?

Thank you so much larsen and Rysc.

Hi,Rysc.You have quite known my design.I do have to use the PLL with inverters.I also belive that 250MHz data flow can be correctly handled. It just should ensure setup and hold condition of the input registers directly associated with input I/O(external 250MHz data flow input port). I mean that four DFFs,which have a clock input of 250MHz(In the file I attached as "SinPout.zip") . After correctly handled,I can use them under 125MHz internally.

But,there is someting boring. All the 250MHz data flow input ports are assigned in bank2,ranged from pin-197 to pin-240,however, on chip RAMs are locate from X17_Y1--X17_Y20. I need 16 blocks of 20 total.So,the route delay from data input can't be almost the same when reach RAMs.Now I still have a little problem about data storage. Is it a fatal problem when QII fits my design? I will attach a shoot screen of time closure floorplan.

By the way,FPGAs' density are increasing.So the performance not the resource usage is most concerned . Then maybe timing constraints should give more attention.How to use assignment editor correctly and high efficiently? Expect QII handbook, are there any other ways or desig reference?

Thank you.

Best Regards.