How to fix timing issues using the timing assignment options?

Thanks for concern ：）

I have changed the FPGA into -6 speed grade.Now,I'm bothered by devices' distinction. The project can run well on one FPGA,but fails on the others.So,I have to adjust timing of every single device. It's indeed a hard work.

Some of friends have also encountered this situation before,in their cases,the distinction just occurs between different batch of FPGA. Unfortunately,I'm suffering on every piece.

Then ,when making your schemes, the distinction also should be considered.