How to fix timing issues using the timing assignment options?

I can't say for sure whether that will meet timing or not. It will probably be close. Since you have clock constraints(done when creating the PLL), Quartus will tell you very directly if it can make timing or not, so you need to implement that portion of the design and see what happens. Since you're capturing data, my guess is you could add another stage of registers between the IO registers and the memory, which adds one latency delay, but should allow you to easily meet internal timing. Usually data capture applications can handle this quite easily, although I don't know if you have latency requirements in your system.