How to fix setup violation for signal tap?

We do not write constraint directly to the signal tap. The Signal tap is bound by the same sdc constraints used for the rest of the design.

The following techniques can help you preserve timing in designs that include the Signal Tap logic analyzer:

-Avoid adding critical path signals to the .stp file.

-Minimize the number of combinational signals you add to the .stp file, and add registers whenever possible.

-Specify an fMAX constraint for each clock in the design.

Reference: https://www.intel.com/content/www/us/en/docs/programmable/683819/23-4/timing-preservation.html

"clk is the clock signal that I set in the signal tap."

>>Do your design only have one clock or multiple clock signal?

There is a possibility that you might using wrong clock to sampling some of the signals,

Regards,

Richard Tan

Kindly share your design by archiving the project (Project > Archive Project) so that I can investigate it further.
What is the Quartus version and the edition (pro/std) used?

If the design cannot be shared publicly, please let me know, and I'll send you an email to facilitate the transfer of files through FTP(Files Transfer Protocol).

Regards,

Richard Tan

Hi,

Do you able to share your design?

Regards,

Richard Tan

Hi Richard,

I cannot share the design for confidential information. I tried to create a simple design but the timing violation does not occur in the simple design. The timing violation occur from the input clock port to the signal tap data signal, what we can try to fix this?

It will be challenging to debug without the design. Here are some debugging steps that we can try to isolate the issue.

-What is the clock frequency that you are using?

Could you check the following when specifying the acquisition clock:

https://www.intel.com/content/www/us/en/docs/programmable/683819/23-4/specifying-the-clock-sample-depth-and.html#mwh1410384497703__section_lr4_qrj_nmb

-Is your design uses a lot of resources? Perhaps try to reduce the numbers of signal tapped to check or reduce the sample depth.

Perhaps isolate the impacted module and try to add signal tap to see if the same timing path still fail.

-Try to add pipeline factor (maximum 5)

https://www.intel.com/content/www/us/en/docs/programmable/683819/23-4/specifying-pipeline-settings.html

Could you share screenshot of the failed timing path's "Data Arrival Path" in the "Data Path" and the "Statistic" Report in the Timing Analyzer?
What is the number of logic levels?

Regards,

Richard Tan

Dropping a note to ask if my last reply was helpful to you?

Do you able to resolve the issue?

Regards,

Richard Tan

Please let me check the suggestion and I will get back to you.

Hi Richard,

The timing violation is actually a hold but not setup. I apologies for the mistake about the setup violation

-Try to add pipeline factor (maximum 5)
It is a clock input signal and not the real data signal. I am not sure can add the pipeline to clock signal or not

Could you share screenshot of the failed timing path's "Data Arrival Path" in the "Data Path" and the "Statistic" Report in the Timing Analyzer?
What is the number of logic levels?

1. Check that Assignments -> Settings -> Fitter has Optimize Hold Timing set to All Paths and Optimize Multi-Corner is checked. This tells the router to add delays to try and meet hold requirements.

2. Have you try to reduce the numbers of signal tapped to check or reduce the sample depth?

3. Given that the design cannot be shared, could we obtain the Database (DB) archive from you? Please note that this won't include any RTL files.

Security Note: A database-only archive does not guarantee protection for sharing your design without sharing your RTL. The RTL Netlist Viewer, Technology Map Viewer, and other views, along with the EDA Netlist Writer, are still available for projects exported using this feature.

You may check this on how to create a DB:

https://www.intel.com/content/www/us/en/docs/programmable/683463/current/creating-database-only-archives.html

p/s: If the design cannot be shared publicly, please let me know, and I'll send you an email to facilitate the transfer of files through FTP(Files Transfer Protocol).

Regards,

Richard Tan