Chris039
Occasional Contributor
Occasional ContributorHow to fix setup violation for signal tap?
Hi, How to fix the setup violation for the signals below? clk is the clock signal that I set in the signal tap. Thanks
Forum Discussion
Chris039Occasional Contributor
Occasional ContributorHi Richard,
The timing violation is actually a hold but not setup. I apologies for the mistake about the setup violation
-Try to add pipeline factor (maximum 5)
It is a clock input signal and not the real data signal. I am not sure can add the pipeline to clock signal or not
Could you share screenshot of the failed timing path's "Data Arrival Path" in the "Data Path" and the "Statistic" Report in the Timing Analyzer?
What is the number of logic levels?
