How to fix setup violation for signal tap?

We do not write constraint directly to the signal tap. The Signal tap is bound by the same sdc constraints used for the rest of the design.

The following techniques can help you preserve timing in designs that include the Signal Tap logic analyzer:

-Avoid adding critical path signals to the .stp file.

-Minimize the number of combinational signals you add to the .stp file, and add registers whenever possible.

-Specify an fMAX constraint for each clock in the design.

Reference: https://www.intel.com/content/www/us/en/docs/programmable/683819/23-4/timing-preservation.html

"clk is the clock signal that I set in the signal tap."

>>Do your design only have one clock or multiple clock signal?

There is a possibility that you might using wrong clock to sampling some of the signals,

Regards,

Richard Tan