How to fix setup violation for signal tap?

It will be challenging to debug without the design. Here are some debugging steps that we can try to isolate the issue.

-What is the clock frequency that you are using?

Could you check the following when specifying the acquisition clock:

https://www.intel.com/content/www/us/en/docs/programmable/683819/23-4/specifying-the-clock-sample-depth-and.html#mwh1410384497703__section_lr4_qrj_nmb

-Is your design uses a lot of resources? Perhaps try to reduce the numbers of signal tapped to check or reduce the sample depth.

Perhaps isolate the impacted module and try to add signal tap to see if the same timing path still fail.

-Try to add pipeline factor (maximum 5)

https://www.intel.com/content/www/us/en/docs/programmable/683819/23-4/specifying-pipeline-settings.html

Could you share screenshot of the failed timing path's "Data Arrival Path" in the "Data Path" and the "Statistic" Report in the Timing Analyzer?
What is the number of logic levels?

Regards,

Richard Tan