How to fix setup violation for signal tap?

1. Check that Assignments -> Settings -> Fitter has Optimize Hold Timing set to All Paths and Optimize Multi-Corner is checked. This tells the router to add delays to try and meet hold requirements.

2. Have you try to reduce the numbers of signal tapped to check or reduce the sample depth?

3. Given that the design cannot be shared, could we obtain the Database (DB) archive from you? Please note that this won't include any RTL files.

Security Note: A database-only archive does not guarantee protection for sharing your design without sharing your RTL. The RTL Netlist Viewer, Technology Map Viewer, and other views, along with the EDA Netlist Writer, are still available for projects exported using this feature.

You may check this on how to create a DB:

https://www.intel.com/content/www/us/en/docs/programmable/683463/current/creating-database-only-archives.html

p/s: If the design cannot be shared publicly, please let me know, and I'll send you an email to facilitate the transfer of files through FTP(Files Transfer Protocol).

Regards,

Richard Tan