How to find Fmax of my design??

please i am really need your help.

i did the follwoing vhdl design:

library ieee;

use ieee.std_logic_unsigned.all;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

entity test is

port( clk : in std_logic;

rst : in std_logic;

input : in std_logic_vector (7 downto 0);

output : out std_logic_vector (7 downto 0));

end entity test;

architecture kkk of test is

signal x0 , x1 , x2 , x3 , x4 , x5 , x6 , x7 : std_logic;

begin

output <= x7 & x6 & x5 & x4 & x3 & x2 & x1 & x0 ;

process (clk,rst)

begin

if (rst='1') then

x0 <= '0'; x1 <= '0'; x2 <= '0'; x3 <= '0'; x4 <= '0'; x5 <= '0'; x6 <= '0'; x7 <= '0';

elsif (clk'event and clk='1') then

x0 <= input(7) AND input(6) AND input(4) AND input(3) AND input(1) AND input(0) ;

x1 <= input(4) AND input(2) ;

x2 <= input(5) AND input(0) ;

x3 <= input(4) AND input(2) ;

x4 <= input(7) AND input(5) ;

x5 <= input(7) AND input(5) AND input(4) AND input(1) ;

x6 <= input(5) AND input(3) AND input(0) ;

x7 <= input(5) AND input(3) AND input(1) AND input(0) ;

end if;

end process;

end architecture kkk;

i am using quartus ii web edition 8.1, i couldn't find the max frequency of the design. i got the following:

Info: No valid register-to-register data paths exist for clock "clk"

Info: tsu for register "x0" (data pin = "input[7]", clock pin = "clk") is 5.000 ns

Info: tco from clock "clk" to destination pin "output[0]" through register "x0" is 8.800 ns

Info: th for register "x1" (data pin = "input[2]", clock pin = "clk") is -0.700 ns

Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning

Info: Quartus II Full Compilation was successful. 0 errors, 2 warnings

i know the report talking about no valid register-to-register.......

i just want to get the value of (output) every clock cycle!

the timing analyzing summery as follow:

Type Slack Required Time ActualTime From To From Clock To Clock

Worst-case tsu N/A None 5.000 ns input[7] x0 -- clk

Worst-case tco N/A None 8.800 ns x0 output[0] clk --

Worst-case th N/A None -0.700 ns input[6] x0 -- clk

Total number of failed paths

Do I must change the design to get Fmax? if yes, that will be little strange for me since the design is working perfectly!

thanks in advance.