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Altera_Forum
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14 years ago

How to find Fmax of my design??

please i am really need your help. i did the follwoing vhdl design: library ieee; use ieee.std_logic_unsigned.all; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; entity...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Thanks jaime.andres for the fast reply, actually I have already did your suggestion before and I got Fmax but, I got another problem in ModelSim.

I should calculate Fmax in FPGA using Quartus and in ASIC using (Synopsys Design Compiler and ModelSim).

If I do your suggestion the Quartus problem will solved but I will get the follwoing Error in ModelSim (in ASIC):

vsim -sdfmax /nlfsr_tb/uut=./SYNOPS/SOURCE/nlfsr_default.sdf work.nlfsr_tb

** Error: (vsim-SDF-3250) ./SYNOPS/SOURCE/nlfsr_default.sdf(60): Failed to find INSTANCE '\output_reg[0] '

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** Error: (vsim-SDF-3250) ./SYNOPS/SOURCE/nlfsr_default.sdf(57): Failed to find INSTANCE '\x0_reg[0] '.

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Which mean ModelSim cannot find INSTANCE for output and x!!!

do you please have a suggestion?

Thanks again