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Altera_Forum
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14 years ago

How to find Fmax of my design??

please i am really need your help. i did the follwoing vhdl design: library ieee; use ieee.std_logic_unsigned.all; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; entity...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Hi

The problem is solved, I just deleted the following line from my script code and every thing work fine:

change_names -rule verilog -hierarchy

Thanks