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Altera_Forum
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14 years ago

How to find Fmax of my design??

please i am really need your help. i did the follwoing vhdl design: library ieee; use ieee.std_logic_unsigned.all; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; entity...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Hi

You dont have the Fmax in the report because the software doesnt find reg-reg paths to analyze, so yes, you have to change the design, Try putting the output instruction inside the process after x7:

...

x7 <= input(5) AND input(3) AND input(1) AND input(0) ;

output <= x7 & x6 & x5 & x4 & x3 & x2 & x1 & x0 ;

...