Honored ContributorSupposed we have CLKA = 100MHz.
Then we generate CLKB = 200MHz based on CLKA, pls see the following picture: http://blogimg.chinaunix.net/blog/upfile2/080109103218.jpg In TimeQuest, how to define CLKB? The phase shift between CLKA & CLKB is based on fitting result, so they are unrelated clocks, right? And so I should cutting the path analysis between them?
Honored ContributorThanks a lot for your answer. In the Altera Max 2 Kit is given the possibility to use a digital PLL named as 72497 and can be found easily at the Library others/maxplus2/74297. The fact is that using this chip is a bit difficult for me because i actually see many Pins and it's a bit terrifying to me. I have still downloaded the datasheets of the 74297 but there are still many issues and many things such as Phase 1 , Phase 2 , Phase B and so on....Any friendly advice with that?
Honored ContributorAn "all digital" PLL like 74297 can only generate a time-discrete output signal with transitions at the input clock active edge. I guess, it's not what you imagine as a PLL clock generator. To learn about 74297 function, you can refer to the datasheet and application notes of the respective TTL IC.
To multiply a clock frequency, generate rational frequency ratios and phase shifted clocks, you need an analog VCO as part of the PLL design. It's provided e.g. with most FPGA, but not with MAX II. Altera once advertised a PLL block for MAX V series, but it hasn't been seen in operation yet, apparently it dropped behind the event horizon... http://www.alteraforum.com/forum/showthread.php?t=27399Honored ContributorThe Problem i face is that the circuit i have attached before produces the frequency i need but not with the correct duty cycle. It is something that i have already measured with the oscilloscope. I repeat that the circuit works but the pulse i get Needs to have a duty cycle at 50 %. Unfortunately the duty cycle seems to be not ok so i do not know if there is a digital way using only gates flip Flops or whatever so that i will not have to Change the development board. But also if things are not so good and there is no possibility to use a digital pll then is there any way to use Phase delays somehow? Regarding the 74297 obviously is not the solution i was looking for so....Keep searching...
Honored ContributorThe reason that i insist trying to produce 20 Mhz this way is that i want to make the circuit completely digital because i have already the solution using an analog circuit....And of course it is better than the analog solution.
Honored ContributorYou didn't post a circuit, but I guess it's a delay chain with XOR gate. This "poor man's" frequency doubler will hardly have a symmetrical duty cycle.
Honored ContributorIt's almost exactly like the circuit of the first Person who opened this Topic. A good solution is the one that is already answered but the fact is that, it cannot run to my web Edition quartus because the message i get is that it is for the statix 2 Family... My aim is to simulate that using my max2 kit and i think that it will not work in my case....
Honored ContributorHonored ContributorHi again, i have the circuit attached in a pdf file. The Problem with it is that i cannot get the desired duty cycle.
Honored ContributorO.K. that's a different version of the said "poor man's" frequency doubler.
I'm not sure if usage of toggle FF instead of a pure logic cell delay line changes much to the basic behaviour, except for a slightly larger delay. To get a 20 MHz output with roughly symmetrical duty cycle, you need 25 ns delay, I guess about 50 to 100 logic cells of MAX II. In HDL, you need a keep synthesis attribute to prevent elimination of the redundant logic cells during synthesis. Don't know how it works in schematic entry. The main disadvantage of logic cell delay chains is their sensitivity to PVT (process, voltage, temperature) variations. The expectable minimum and maximum delay (fast and slow "corner") have an about 1:2 ratio, a designed duty cycle of 50% could be 35 or 70% as well.Honored ContributorThanks a lot for the help...You mentioned something which has to do with the hdl. You probably mean vhdl. The circuit i have is a bit bigger than the one i have already shown you so and i do not know anything from vhdl....So a possible solution is to apply that kind of method in order to achieve it...Correctly?
