How to define clock generated by the other clock?

An "all digital" PLL like 74297 can only generate a time-discrete output signal with transitions at the input clock active edge. I guess, it's not what you imagine as a PLL clock generator. To learn about 74297 function, you can refer to the datasheet and application notes of the respective TTL IC.

To multiply a clock frequency, generate rational frequency ratios and phase shifted clocks, you need an analog VCO as part of the PLL design. It's provided e.g. with most FPGA, but not with MAX II. Altera once advertised a PLL block for MAX V series, but it hasn't been seen in operation yet, apparently it dropped behind the event horizon...

http://www.alteraforum.com/forum/showthread.php?t=27399