How to define clock generated by the other clock?

O.K. that's a different version of the said "poor man's" frequency doubler.

I'm not sure if usage of toggle FF instead of a pure logic cell delay line changes much to the basic behaviour, except for a slightly larger delay. To get a 20 MHz output with roughly symmetrical duty cycle, you need 25 ns delay, I guess about 50 to 100 logic cells of MAX II. In HDL, you need a keep synthesis attribute to prevent elimination of the redundant logic cells during synthesis. Don't know how it works in schematic entry. The main disadvantage of logic cell delay chains is their sensitivity to PVT (process, voltage, temperature) variations. The expectable minimum and maximum delay (fast and slow "corner") have an about 1:2 ratio, a designed duty cycle of 50% could be 35 or 70% as well.