How to define clock generated by the other clock?

I think Altera talks about this in the following doc:

http://www.altera.com/literature/hb/qts/qts_qii53019.pdf

on page 7-19. By default the two clocks will be considered related in TimeQuest. If the circuit is designed such that they are assumed unrelated, then a false path can be assigned between them.

Sorry, the web link seem to be damaged.

Pls check it.

If possible, could send me the datasheet to my mail box directly:

CaiWG.NiosII@gmail.com

Thanks again!

Hi, I have found the related info in QuartusII 7.1 handbook.

In fact, I have read it before, but I can't find any answer for my question above.

Just for the simple question above, could you answer directly, I'm a little confused.

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The phase shift between CLKA & CLKB is based on fitting result, so they are unrelated clocks, right? And so I should cutting the path analysis between them?

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I myself think that:

Thouth the phase shift between CLKA & CLKB is based on fitting result, but TimeQuest should also know the phase shift, so it should create tge generated clock automatically.

Thanks...

Isn't that a divide-by-2, not a multiply-by-2, circuit that you showed? CLKB will be half the frequency (twice the period) of CLKA.

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I myself think that:

Thouth the phase shift between CLKA & CLKB is based on fitting result, but TimeQuest should also know the phase shift, so it should create tge generated clock automatically.

--- Quote End ---

Yes, TimeQuest knows the delay the register and routing creates between CLKA and CLKB, but TimeQuest does not know the effect on the frequency. You use a generated clock for CLKB to tell TimeQuest how to compute the CLKB frequency from the upstream CLKA frequency. You do not specify a phase shift--TimeQuest adds a clock network delay automatically.

Do not use a circuit like this if you still have a PLL available to create CLKB. Another option is to use a divide-by-2 clock enable instead of a derived clock.

If you do create a clock with logic this way, be aware of the caveats in my posts at http://www.alteraforum.com/forum/showthread.php?t=754. As discussed in my first post in that thread, it is OK if CLKB uses global routing, you set up your design so that no data paths between the CLKA and CLKB domains are synchronous, and you use set_false_path or set_clock_groups to cut analysis on the cross-domain data paths.

David,

I am not sure if anybody gave you the actual answer to your specific question. The answer is very simple:

CLKA and CLKB are in fact related, and should not be cut unless you have a specific reason to do so (like a FIFO to synch up the transfer). The delay between CLKA and CLKB is modeled as clock latency (both by TimeQuest and Classic). So, all you need to do is:

create_clock -period 10 CLKA

create_generated_clock -divide 2 -source CLKA CLKB

TimeQuest will then do everything right. If you want to then see the details of the analysis, remember to use "-detail full_path" when running report_timing. That will show you the delays between CLKA and CLKB.

You can see the example at:

http://www.altera.com/support/examples/timequest/exm-tq-generated-clock.html

great answer!!

That is what I want.

Wow, I get a big fish again, the more important is I get two fishing technologies. :)

I always think that fishing is much more important than fishes.

Thanks all of you & altera forum from my deep heart!

I am just thinking the following question:

Why I can't find such important info from Altera's handbook directly, it's very important for newers, isn't it?

I have the similar situation, but CLKB is not connected to FPGA pin:

https://www.alteraforum.com/forum/attachment.php?attachmentid=8239

Quartus 12.1 gives Warning (332060): Node: inst33 was determined to be a clock but was found without an associated clock assignment.

What should be done to get rid of this warning?

What associated clock assignment should be set in .sdc file for CLKB?

P.S.

Example at Figure 1. "Divide by 2 Generated Clock" ( create_generated_clock_ex1.qar (http://www.altera.com/support/examples/download/create_generated_clock_ex1.qar) ) in the above mentioned Altera document http://www.altera.com/support/examples/timequest/exm-tq-generated-clock.html after being compiled produces the same

Warning (332060): Node: div2reg was determined to be a clock but was found without an associated clock assignment.

Hi to everyone. Unfortunately i am a new guy and i have recently started using the FPGAs. I have also the same problem which is how to get double output frequency from an input clock. Unfortunately i have tried also this method and the results are that in my case i can really double the frequency but the problem that i now face is that i cannot make a clear pulse around 50 % Duty cycle. Any idea if is this possible. The frequency input of my system is only 10 MHz and the target frequency is 20MHz which are generally considered to be small frequencies. Please has anyone any idea on how to achieve it? I have attached a picture of the circuits i made and botha work without the desired duty cycle.

(PS* i use only the schematic designs without knowing anything from Verilog or VHDL) :(

Generating clocks like the above is a very bad idea. For a start no one corrects the OP on his fundamental mistake that ClkB is actually CLKA/2, not CLKA x2.

But generating clocks with logic for anything except slow frequencies (like < 1MHz) will be prone to timing variations from different compilations, high fanout skew, temperature fluctuation. Basically, everything you cannot control.

You should use a PLL to generate any clocks, as you have full control over phase, fanout skew will be close to 0 and it will not vary with temperature. And you will get a 50% duty cycle. So Use a PLL (available in the megawizard).