How to define clock generated by the other clock?

Generating clocks like the above is a very bad idea. For a start no one corrects the OP on his fundamental mistake that ClkB is actually CLKA/2, not CLKA x2.

But generating clocks with logic for anything except slow frequencies (like < 1MHz) will be prone to timing variations from different compilations, high fanout skew, temperature fluctuation. Basically, everything you cannot control.

You should use a PLL to generate any clocks, as you have full control over phase, fanout skew will be close to 0 and it will not vary with temperature. And you will get a 50% duty cycle. So Use a PLL (available in the megawizard).