How to define clock generated by the other clock?

Hi to everyone. Unfortunately i am a new guy and i have recently started using the FPGAs. I have also the same problem which is how to get double output frequency from an input clock. Unfortunately i have tried also this method and the results are that in my case i can really double the frequency but the problem that i now face is that i cannot make a clear pulse around 50 % Duty cycle. Any idea if is this possible. The frequency input of my system is only 10 MHz and the target frequency is 20MHz which are generally considered to be small frequencies. Please has anyone any idea on how to achieve it? I have attached a picture of the circuits i made and botha work without the desired duty cycle.