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Altera_Forum's avatar
Altera_Forum
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15 years ago

How to cut clock speed in half?

Im using the latest web edition of Quartus II and am only a few days old to Verilog HDL. I have been able to program the Cyclone II FPGA to blink an LED, woohoo! I am now trying to use some other code that is the beginning of creating a VGA signal. My problem is that the example code that im using to create H and V sync is designed for a 25mhz processor and my board is using a 50mhz crystal. What do I need to change about the 'input clk' command to cut the clock rate in half?

Thanks

Jason 


module hvsync_generator(clk, vga_h_sync, vga_v_sync, inDisplayArea, CounterX, CounterY);
input clk;
output vga_h_sync, vga_v_sync;
output inDisplayArea;
output  CounterX;
output  CounterY;
//////////////////////////////////////////////////
reg  CounterX;
reg  CounterY;
wire CounterXmaxed = (CounterX==10'h2FF);
always @(posedge clk)
if(CounterXmaxed)
 CounterX <= 0;
else
 CounterX <= CounterX + 1;
always @(posedge clk)
if(CounterXmaxed) CounterY <= CounterY + 1;
reg vga_HS, vga_VS;
always @(posedge clk)
begin
 vga_HS <= (CounterX==6'h2D); // change this value to move the display horizontally
 vga_VS <= (CounterY==500); // change this value to move the display vertically
end
reg inDisplayArea;
always @(posedge clk)
if(inDisplayArea==0)
 inDisplayArea <= (CounterXmaxed) && (CounterY<480);
else
 inDisplayArea <= !(CounterX==639);
 
assign vga_h_sync = ~vga_HS;
assign vga_v_sync = ~vga_VS;
endmodule

5 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    One way would be to use a PLL to produce a 25 MHz clock from the 50 MHz clock. Check the megafunctions.

    Another good way would be to use a clock enable.

    reg clk_enable;

    always @ (posedge clk) clk_enable <= ! clk_enable;

    ^^ enable is "1" just for every other clock

    Then you wrap arround every piece of code you need to run at 25 MHz like this

    always @ (posedge clk)

    begin

    if (clk_enable) begin

    // Your code goes here

    end

    end
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    Thanks for the help. Is the below code then the correct usage of your second suggestion? Or could I inefficiently run the entire code at 25mhz as that is all that is needed and perhaps easier? 

    
module hvsync_generator(clk, vga_h_sync, vga_v_sync, inDisplayArea, CounterX, CounterY);
input clk;
output vga_h_sync, vga_v_sync;
output inDisplayArea;
output  CounterX;
output  CounterY;
//////////////////////////////////////////////////
reg clk_enable; ADDED LINE
always @ (posedge clk) clk_enable <= ! clk_enable; ADDED LINE
reg  CounterX;
reg  CounterY;
wire CounterXmaxed = (CounterX==10'h2FF);
always @(posedge clk)
if(CounterXmaxed)
 CounterX <= 0;
else
 CounterX <= CounterX + 1;
always @(posedge clk)
if(CounterXmaxed) CounterY <= CounterY + 1;
reg vga_HS, vga_VS;
always @(posedge clk)
begin
if (clk_enable) begin ADDED LINE
 vga_HS <= (CounterX==6'h2D); // change this value to move the display horizontally
 vga_VS <= (CounterY==500); // change this value to move the display vertically
end ADDED LINE
end
reg inDisplayArea;
always @(posedge clk)
if(inDisplayArea==0)
 inDisplayArea <= (CounterXmaxed) && (CounterY<480);
else
 inDisplayArea <= !(CounterX==639);
 
assign vga_h_sync = ~vga_HS;
assign vga_v_sync = ~vga_VS;
endmodule
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    Another idea is to use an enable and "enable" it on every other other clock. This way you keep the same clock, and don't have to slow down your circuit. However, if you can get by with 25MHz like you mentioned that's always an option. Sometimes KISS is the best way to accomplish something, unless you have time to experiment and want to try a few alternatives.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    If the 50 MHz input clock isn't used in the design, a DFF clock divider won't cause any timing issues. In this case, it's the most simple option.