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Altera_Forum
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15 years ago

How to cut clock speed in half?

Im using the latest web edition of Quartus II and am only a few days old to Verilog HDL. I have been able to program the Cyclone II FPGA to blink an LED, woohoo! I am now trying to use some other cod...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

If the 50 MHz input clock isn't used in the design, a DFF clock divider won't cause any timing issues. In this case, it's the most simple option.