I create my PCIe project based on Wiki's examples, removed the DDR3 and added FIFO inside Qsys. I can't connect my FIFOs to mSGDMA after i added them to my Qsys. I attached the project.

Hi Jerry, you are trying to write to an output. The dma_write_master is designed to write streaming Data into a memory. For example your Host-RAM. But you connected its Memory Mapped Master to the Output-Port of fifo_0. I don't know exactly how you want to design this, but I think you want this: [outside logic] ---> [MM or ST IN ---> FIFO ---> ST OUT] ---> [ST IN ---> DMA_WRITE_MASTER ---> MM OUT] ---> [MM IN (txs) ---> PCIE_HIP ---> RX/TX_OUT] ---> [Your Host] Also connect the CSR-Registers directly to one of your PCIe-BARs. You can read and write them via DMA, but it does not make sense because a direct access will be much faster. Use DMA only for "large" data access. Try this. Do you need to write data from your host to your FPGA? If not, remove the dma_read_master. Another very good idea: If you edit the Verilog-Code of the dma_write_master, you can route out the fill level of its data-fifo. By this way you can throw away any other fifo and work directly with the fifos of the write_master.

--- Quote Start --- Hi Jerry, you are trying to write to an output. The dma_write_master is designed to write streaming Data into a memory. For example your Host-RAM. But you connected its Memory Mapped Master to the Output-Port of fifo_0. I don't know exactly how you want to design this, but I think you want this: [outside logic] ---> [MM or ST IN ---> FIFO ---> ST OUT] ---> [ST IN ---> DMA_WRITE_MASTER ---> MM OUT] ---> [MM IN (txs) ---> PCIE_HIP ---> RX/TX_OUT] ---> [Your Host] Also connect the CSR-Registers directly to one of your PCIe-BARs. You can read and write them via DMA, but it does not make sense because a direct access will be much faster. Use DMA only for "large" data access. Try this. Do you need to write data from your host to your FPGA? If not, remove the dma_read_master. Another very good idea: If you edit the Verilog-Code of the dma_write_master, you can route out the fill level of its data-fifo. By this way you can throw away any other fifo and work directly with the fifos of the write_master. --- Quote End --- Hi Steffen, Yes, i need put my data from my logic to my host, and receive a little data which is of configuration for my system from my host. I'll change it according you advised.

--- Quote Start --- Hi Jerry, you are trying to write to an output. The dma_write_master is designed to write streaming Data into a memory. For example your Host-RAM. But you connected its Memory Mapped Master to the Output-Port of fifo_0. I don't know exactly how you want to design this, but I think you want this: [outside logic] ---> [MM or ST IN ---> FIFO ---> ST OUT] ---> [ST IN ---> DMA_WRITE_MASTER ---> MM OUT] ---> [MM IN (txs) ---> PCIE_HIP ---> RX/TX_OUT] ---> [Your Host] Also connect the CSR-Registers directly to one of your PCIe-BARs. You can read and write them via DMA, but it does not make sense because a direct access will be much faster. Use DMA only for "large" data access. Try this. Do you need to write data from your host to your FPGA? If not, remove the dma_read_master. Another very good idea: If you edit the Verilog-Code of the dma_write_master, you can route out the fill level of its data-fifo. By this way you can throw away any other fifo and work directly with the fifos of the write_master. --- Quote End --- Hi Steffen, I read your comments carefully, do you mean if i want put my data to Qsys, i should connect the FIFO-out to DMA write master? Can't connect it to DMA read master? But, when connect FIFO's ST out to DMA write master, qsys will report me one error:"The source has 256 bits per symbol, while the sink has 8" as attached shows.

Hi Jerry, sorry for the late answer. The Write-Master writes to your Host-Memory. It reads from your Fifo. The Read-Master reades from your Host-Memory. It writes to a (whatever) Data Sink. This is, why you have to connect the Output of your Fifo (Streaming source) to the Write-Master (Streaming sink). When you have a mismatch in data-width of write-master and fifo, you should correct this by editing the parameters of those cores. If you want to use a 256Bit fifo, you should also configure the write-master with a 256Bit fifo. At the moment the write-master fifo is 8Bit. Of course QSYS gives you this mismatch error. Just double click the write master and configure the data fifo to 256Bit.

--- Quote Start --- Hi Jerry, sorry for the late answer. The Write-Master writes to your Host-Memory. It reads from your Fifo. The Read-Master reades from your Host-Memory. It writes to a (whatever) Data Sink. This is, why you have to connect the Output of your Fifo (Streaming source) to the Write-Master (Streaming sink). When you have a mismatch in data-width of write-master and fifo, you should correct this by editing the parameters of those cores. If you want to use a 256Bit fifo, you should also configure the write-master with a 256Bit fifo. At the moment the write-master fifo is 8Bit. Of course QSYS gives you this mismatch error. Just double click the write master and configure the data fifo to 256Bit. --- Quote End --- Hi Steffen, Thanks for you reply, it's clear now for me, and i know how to expose ports and connect inside Qsys. However, as attached file shows, the DMA write-master(ST sink) data width is already 256-bits.

How to connect my FIFO to mSGDMA inside Qsys?

16 Replies

Altera_Forum
Honored Contributor
11 years ago
Qsys will insert data width adapters when necessary to adapt wide masters to narrow slaves or narrow masters to wide slaves. Depending on the topology of your design you might end up with a bunch of adapters in your design like Steffen said so to control that what you can do is place the 128-bit slaves behind a 128-bit memory mapped bridge and connect the 256-bit master to the bridge. That way the only adapter that is needed is between the 256-bit master and the 128-bit bridge slave port. If the master was only connected to these 128-bit slaves I think Qsys is smart enough to adapt on the master side thereby giving you the same effect (only one adapter).

The idea with Avalon is as long as you design masters and slaves within the spec, then you don't have to worry about the glue that connects them. Qsys will adapt data widths, burst sizes, burst capabilities, signal polarity, pipelined read capabiliities, etc... for you.
Altera_Forum
Honored Contributor
11 years ago
--- Quote Start ---
Qsys will insert data width adapters when necessary to adapt wide masters to narrow slaves or narrow masters to wide slaves. Depending on the topology of your design you might end up with a bunch of adapters in your design like Steffen said so to control that what you can do is place the 128-bit slaves behind a 128-bit memory mapped bridge and connect the 256-bit master to the bridge. That way the only adapter that is needed is between the 256-bit master and the 128-bit bridge slave port. If the master was only connected to these 128-bit slaves I think Qsys is smart enough to adapt on the master side thereby giving you the same effect (only one adapter).

The idea with Avalon is as long as you design masters and slaves within the spec, then you don't have to worry about the glue that connects them. Qsys will adapt data widths, burst sizes, burst capabilities, signal polarity, pipelined read capabiliities, etc... for you.
--- Quote End ---

Hi BadOmen,

Did you mean Qsys will add those width adapters automatically? User doesn't need to involve it?
Altera_Forum
Honored Contributor
11 years ago
Sorry was out on vacation. Yes Qsys will perform many types of adaptation between masters and slaves. When you design a master or slave you design it using the Avalon/AXI spec and not worrying about other IP connecting to it.
Altera_Forum
Honored Contributor
11 years ago
--- Quote Start ---
Sorry was out on vacation. Yes Qsys will perform many types of adaptation between masters and slaves. When you design a master or slave you design it using the Avalon/AXI spec and not worrying about other IP connecting to it.
--- Quote End ---

Hi BadOmen,

It's ok! I'm designing my logic to put/take data to/from my Qsys system, which include PCIe interface. So this is why i posted this question.
Altera_Forum
Honored Contributor
11 years ago
Can someone help me this: http://www.alteraforum.com/forum/showthread.php?t=47763&p=196511
Altera_Forum
Honored Contributor
10 years ago
--- Quote Start ---
I didn't read the entire thread but sounds like you want to expose the write master streaming port to logic outside of Qsys. You can do that by clicking on the write master data streaming port twice in the export column and it should allow you to assign a name to this port which will show up at the top level of the Qsys system.

The issue mentioned at the top sounds a either a mismatch in data widths or a mismatch with symbol widths. The mSGDMA deals with symbols of 8-bit since the symbols have to land in byte lanes in memory after the symbols get reversed. So if you had a 32-bit write master and the streaming data comes in as D[31:0] = 32'hDEADBEEF you will see the symbols get reversed and written as 32'hEFBEADDE out to memory. Avalon-MM uses little endian byte ordering while Avalon-ST uses network order (a.k.a. big endian) so that's why the symbols get shuffled around internally. If you are connecting a FIFO with a different symbol size I would just create a little gasket that has an Avalon-ST source and sync pair with the source using 8-bit symbols and the sink using whatever your FIFO uses as a symbol size to adapt between the symbol sizes. This gasket is just wires so you are simply tricking Qsys into letting you integrate these blocks together.

I have been keeping the mSGDMA up to date on the wiki but I recommend using the cores that appear in Qsys starting in 14.0.
--- Quote End ---

Hi BadOmen,
I don't understand this - I want to connect my streaming PCIe port to a msgdma, and I can't, because the PCIe has 64 bits width, the msgdma has 64 bits width but only shows 8, because it has to do byte reordering (if I understand you correctly). Why? Can't it just assume that if you wanted byte reordering you'd do that, and it can just connect two 64 bit buses together? Equally, I don't really understand your "gasket" - doesn't one clock have to run 8 times faster if it's swapping from 64 bits in to 8 bits out?

Thanks,
Simon

Forum Discussion

How to connect my FIFO to mSGDMA inside Qsys?

16 Replies

Recent Discussions

how to reduce clock skew between synchronous clock

Quartus 13.1 including Signal Tap License

I do not get an eMail with the generated license file

Installer cannot establish connection with SSL error

Quartus 20.1std compilation fails for Quartus map - Device 10AS057K2F40I1SG