How to connect my FIFO to mSGDMA inside Qsys?

Qsys will insert data width adapters when necessary to adapt wide masters to narrow slaves or narrow masters to wide slaves. Depending on the topology of your design you might end up with a bunch of adapters in your design like Steffen said so to control that what you can do is place the 128-bit slaves behind a 128-bit memory mapped bridge and connect the 256-bit master to the bridge. That way the only adapter that is needed is between the 256-bit master and the 128-bit bridge slave port. If the master was only connected to these 128-bit slaves I think Qsys is smart enough to adapt on the master side thereby giving you the same effect (only one adapter).

The idea with Avalon is as long as you design masters and slaves within the spec, then you don't have to worry about the glue that connects them. Qsys will adapt data widths, burst sizes, burst capabilities, signal polarity, pipelined read capabiliities, etc... for you.