New ContributorHello
When using the PLL_ADC_internal followed by a ClockControlBlock which goes to the internal Dual-ADC from the Max10, it is not possible to connect it as shown below.
If so, Quartus can't fit it. Now, when this ClockControlBlock is deleted it works. The reason for this Clock-ControlBlock is to disable the PLL_ADC when not used.
Question:
Thanks
ContributorPut the PLL in reset. Given you don't appear to use the clock out of the PLL for anything else I can't see this being a problem.
Gating a clock to an internal block (internal ADC) may well be something the MAX10 routing cannot accommodate. If this was to an external pin I wouldn't anticipate a problem.
Cheers,
Alex
New ContributorThe disadavantage of a reset is, that it takes much longer until the PLL is working again. Therefore I would like to use a ClockControl. Is this configuration simply not possible??
ContributorIf Quartus says 'no' then I suspect it's not possible, although I am a little surprised. I may well try this later...
If you can feed the clock off the device and back in on another pin I'm suspect you'll be able to realise a solution.
Cheers,
Alex
New Contributorfor whatever reason I can't use the Clock-Controlblock in between the PLL and the Max10 ADC I will try to use the 'reset' of the PLL as you mentioned. Do you know how to assign
for example PLL1 with FPGA clock input CLK1?
