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Norick's avatar
Norick
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7 years ago

How to connect a Clock-Controlblock with a ADC-PLL?

Hello When using the PLL_ADC_internal followed by a ClockControlBlock which goes to the internal Dual-ADC from the Max10, it is not possible to connect it as shown below. If so, Quartus can't...
a_x_h_75's avatar
a_x_h_75
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7 years ago

If Quartus says 'no' then I suspect it's not possible, although I am a little surprised. I may well try this later...

If you can feed the clock off the device and back in on another pin I'm suspect you'll be able to realise a solution.

Cheers,

Alex

Norick's avatar
Norick
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7 years ago

for whatever reason I can't use the Clock-Controlblock in between the PLL and the Max10 ADC I will try to use the 'reset' of the PLL as you mentioned. Do you know how to assign

for example PLL1 with FPGA clock input CLK1?