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Altera_Forum's avatar
Altera_Forum
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13 years ago

How to configure when generate JIC file

There are two same FPGA in my JTAG chain, and these two FPGA will be configured with same configuration file.

Ｉwant to download the EPCS device using JTAG, so i generate a JIC configuration file. The paramters setting are as attached file. But there is a error information when download this jic file, why?

Error information as below,

"Error (209031): Device chain in Chain Description File does not match physical device chain -- expected 1 device(s) but found 2 device(s)."

5 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    Hm. I'm not sure, if this configuration is supported by indirect JTAG programming. Did you find any hints in the device manual?

  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    --- Quote Start ---

    Hm. I'm not sure, if this configuration is supported by indirect JTAG programming. Did you find any hints in the device manual?

    --- Quote End ---

    I did like this on my another board. But, there is only one FPGA in the JTAG chain.

    There two FPGAs on current board's jtag chain with one EPCS device. It seems the jtag detect 2 hardware on the chain when downloading JIC file thru jtag. So the programmer would give out the error information if i downloaded using the converted JIC file as my previous post's settings.

    These 2 FPGAs share one EPCS, so do i need to set these two device as flash loader? But the converter only permit adding single flash loader.
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    I don't doubt, that SFL could work for a multiple FPGA configuration setup logically. But apparently the Quartus programmer isn't prepared for this case, at least it's not mentioned anywhere in the documentaton. For this case I asked if you seen a reference in the documents?

    You should preferably file a support request to ask Altera.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    --- Quote Start ---

    I don't doubt, that SFL could work for a multiple FPGA configuration setup logically. But apparently the Quartus programmer isn't prepared for this case, at least it's not mentioned anywhere in the documentaton. For this case I asked if you seen a reference in the documents?

    You should preferably file a support request to ask Altera.

    --- Quote End ---

    Hi FvM:

    The issue can be closed now. I made a mistake before i post this thread. I tried to download jic yesterday, and i succeed. Anyway, thank you very much!

    The mistake i made is that i download the jic like single device on the jtag chain, as first attached jpg file shows. The proper opaeration is add all rest devces' sof file into programmer besides the flash loader's jic when downloading, just as the sencond attached jpg file shows.
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    Hello Jerry,

    Good to know, that this configuration (SFL with multiple FPGA) works.

    rank