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I don't doubt, that SFL could work for a multiple FPGA configuration setup logically. But apparently the Quartus programmer isn't prepared for this case, at least it's not mentioned anywhere in the documentaton. For this case I asked if you seen a reference in the documents?
You should preferably file a support request to ask Altera.
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Hi FvM:
The issue can be closed now. I made a mistake before i post this thread. I tried to download jic yesterday, and i succeed. Anyway, thank you very much!
The mistake i made is that i download the jic like single device on the jtag chain, as first attached jpg file shows. The proper opaeration is add all rest devces' sof file into programmer besides the flash loader's jic when downloading, just as the sencond attached jpg file shows.
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