How to change a library refence in modelsim?

Okay, I managed to resolve your issue. The instance of the FloatLn function has in its component declaration the sclr port, where as in the component port map the said 'sclr' port is missing and in the VHDL source also the port is not there.

You just need to comment out the sclr port in the FloatLn.vhd file as shown below:

COMPONENT altsquare

GENERIC

(

DATA_WIDTH : NATURAL;

PIPELINE : NATURAL;

REPRESENTATION : STRING := "UNSIGNED";

RESULT_ALIGNMENT : STRING := "LSB";

RESULT_WIDTH : NATURAL;

lpm_type : STRING := "altsquare"

);

PORT

(

aclr : IN STD_LOGIC := '0';

clock : IN STD_LOGIC := '1';

data : IN STD_LOGIC_VECTOR(DATA_WIDTH-1 DOWNTO 0);

ena : IN STD_LOGIC := '1';

result : OUT STD_LOGIC_VECTOR(RESULT_WIDTH-1 DOWNTO 0)

--sclr : IN STD_LOGIC := '0'

);

end component;

squarer : altsquare

GENERIC MAP (

DATA_WIDTH => 13,

PIPELINE => 1,

REPRESENTATION => "UNSIGNED",

RESULT_ALIGNMENT => "MSB",

RESULT_WIDTH => 14

)

PORT MAP ( -- No sclr port here

aclr => aclr,

clock => clock,

data => squarerIn,

ena => clk_en,

result => wire_squarer_result

);

Recompile all the files/design after making this edit. Then simulate it.

I guess this issue may need to be fixed by Intel(Altera).

As per your question - if you are using modelsim altera edition - you dont. The libraries are already mapped.

Those libraries are the for when you use a simulator without the libraries already mapped. eg. Modelsim SE, Questa, Active HDL etc.

In that case, you will need to create a library called altera_mf, then compile <Quartus II installation directory>\eda\sim_lib\altera_mf.vhd into that library.

console commands:

vlib altera_mf

vcom -work altera_mf <quartus>\eda\sim_lib\altera_mf.vhd

vcom -work altera_mf <quartus>\eda\sim_lib\altera_mf_components.vhd

Are you trying to do a post synthesis simulation or RTL simulation? If you're doing a RTL simulation you need to include the altera_mf and any other altera library in the VHDL code.

library altera_mf;

Use altera_mf.all;

You could try using the above statements in the VHDL code. Open the altera_mf library source code and see under which component is the module in question. include that in the "USE altera_mf.<component_name>.all;

If this doesn't work, then what you can try is to compile the altera_mf VHDL sources/library into your work library. This will include all of the required modules and your design will compile & simulate.

If you're doing a post-synthesis simulation the libraries will get used by default.

Hello Abraham,

I do not understand your answer;

Altera & modelsim have installed different versions of the "altSquare" IP block on my system. All of tem reside in files called altera_mf.vhd with component declarations in altera_mf_components.vhd. (all of them have identical names, but they reside in different directories)

Modelsim is referring to the wrong verions so the statement

use altera_mf.all makes modelsim use a version of altSquare as part of altera_mf that is not compatible with an other ip block from altera that I use (calculation of logarithm). The problem is in the signature of the blocks.

I know where the right version of altera_mf stands, but I cannot change the directory reference in modelsim successfully. (So the statement use altera_mf.all needs to make modelsim include another file (library) with the same name coming from a different directory, it is not that i am missing use altera_mf.all, the statement ends up compiling the wrong file with the right name.)

Best regards,

Johi.

hi Johi,

Can you please check the each & every port & ports type of the component instance 'squarer' & corresponding entity?

Especially sclr port.

Let me know if this has helped resolve the issue you are facing or if you need any further assistance.

Best Regards

Vikas Jathar

(This message was posted on behalf of Intel Corporation)

Okay, let me clear things up a bit.

#1. MentorGraphics who is the developer of ModelSim does not and will not include any EDA vendor like Intel(Altera)/Xilinx FPGA libraries by default in their ModelSim or QuestaSim products. They only include standard IEEE VHDL & Verilog libraries.

#2. The version of ModelSim that is shipped along with Quartus has been customized by Intel (Altera) by adding their respective pre-compiled FPGA and device libraries that are needed for simulation. These are provided so that users need not compile the entire FPGA and device libraries again.

#3. The Quartus tools come with two versions of the libraries. One that is located in the eda/sim_libs is meant only for Simulation purposes. While the other library is meant for synthesis.

Do not use the synthesis library for simulation purposes. Use only the simulation libraries for RTL simulations.

Modules that are present in the sim libraries and the synthesis libraries are different in terms of ports as well as timing and other information. Simulation libraries may contain the basic functional interfaces that are needed for simulation , where as the synthesis libraries will contain all of the port information for that IP/block. This will also include interfaces/ports that you are not using in the design.

#4. When creating designs which use IPs or Megafunctions, you have to generate the simulation model for the IP or megafunction that you are using. This will generate the required simulation models for the IPs/blocks used and you can compile them along with the rest of the RTL for functional simulation.

#5. When you create a variation of a Megafunction/IP block, always create the simulation models as well as the instantiation templates. This way the tool will create a template that is customized as per your requirements.

Please do not edit the simulation or synthesis models located in the quartus folders as it would lead to errors when generating the same IP blocks later. As stated above, always generate a simulation model for the IPs that you're using and compile them along with your design. Quartus will also generate a script that you can use to compile your design.

Hello Abraham, Hello Vicky,

I did not think that Abraham's advice would solve the issue, however I took it very serious; I made a brand new demo project, I let Quartus generate all Ip simulation blocks and launched modelsim-altera (rtl) from Quartus: Identical Modelsim error:

Loading altera_mf.altsquare(altsquare_syn)

# ** Error: (vsim-3732) C:/FpgaProjects/Q17/DE10_STD_AUTO_SIMU/FloatLn.vhd(5922): No default binding for component instance 'squarer'.

# The following component port is not on the entity:

# sclr

# Time: 0 ps Iteration: 0 Instance: /ent_de10_std_auto_simu_bench/main/psd_03_14_floatLn/FloatLn_altfp_log_qca_component/squarer File: C:/intelFPGA_lite/17.1/modelsim_ase/win32aloem/../altera/vhdl/src/altera_mf/altera_mf.vhd

# Error loading design

# Error: Error loading design

My demo project instantiaties 2 Intel/Altera Ip components:

psd_03_14_conv : component intToFloat -- ALTFP_CONVERT ip

PORT map

(

clock =>clock_50,

dataa =>psd03_14_i,

result =>psd03_14_f

);

psd_03_14_floatLn : component FloatLn -- ALTFP_LOG ip

PORT map

(

clock =>clock_50,

data =>psd03_14_f,

result =>psd03_14_ln_f

);

If I comment out FloatLn instantiation (ALTFP_LOG based), compilation, simulation run smooth, no problem at all.

When I ad FloatLn I get the error described above in modelsim. So I doubt that my way of work is the culprit.

To me what is happening points more in the direction of an altera/intel bug? But I am not sure, since I am not an expert.

Analysis (1):

ALTFP_LOG instantiates in line 5910 (FloatLn is Ip generation of ALTFP_LOG)

squarer : altsquare

GENERIC MAP (

DATA_WIDTH => 13,

PIPELINE => 1,

REPRESENTATION => "UNSIGNED",

RESULT_ALIGNMENT => "MSB",

RESULT_WIDTH => 14

)

PORT MAP (

aclr => aclr,

clock => clock,

data => squarerIn,

ena => clk_en,

result => wire_squarer_result

);

Analysis (2): altsquare ip has various versions on my system (only 1 version of quartus was installed),

altsquare is defined in altera_mf.vhd (c:\...\modelsim_ase\vhdl\src\altera_mf) at line 48852

altsquare is also defined in altera_mf.vhd (c:\..\quartus\eda\sim_lib) at line 48852

entity altsquare is /../

-- PORT DECLARATION

port

(

data : in std_logic_vector (data_width - 1 downto 0);

clock : in std_logic := '0';

ena : in std_logic := '1';

aclr : in std_logic := '0';

result : out std_logic_vector (result_width - 1 downto 0)

);

end altsquare;

-- END OF ENTITY

=> Both definitions are EQUAL = OK

Analysis (3) : But the component delcarations are different.

altsquare is defined in altera_mf_components.vhd (c:\..\altera_mf) at line 2972:

component altsquare

port(

aclr : in std_logic := '0';

clock : in std_logic := '1';

data : in std_logic_vector(data_width-1 downto 0);

ena : in std_logic := '1';

result : out std_logic_vector(result_width-1 downto 0)

sclr : in std_logic := '0'

);

altsquare is also defined in altera_mf_components.vhd (c:\..\sim_lib) at line 1643

component altsquare

port(

aclr : in std_logic := '0';

clock : in std_logic := '1';

data : in std_logic_vector(data_width-1 downto 0);

ena : in std_logic := '1';

result : out std_logic_vector(result_width-1 downto 0)

);

end component;

So the sclr port is added to the signature of the block in altera_mf_components in the directory altera_mf, but not in sim_lib,

the implementation of the components is identical. I do not consider myself an expert, but wether we are simulating RTL or Gate level,

I would expect that the block signatures in altera_mf_components (component definition) and in (altera_mf) (implementation) need to be equal.

So I am not surprised that modelsim, as it refers to the directory altera_mf, signals an error.

My initial question remains on the table: how to I change the library references of altera_mf & altera_components_mf to the right directories?

Possibly there is an other solution, I 'm open to suggestions, but since it is IP code referring to IP code, my options are limited.

To support my thesis, there is an Altera Quartus 13.1 help web page:

https://www.intel.com/content/www/us/en/programmable/quartushelp/13.1/mergedProjects/hdl/mega/mega_file_altsquare.htm

That clearly states:

"To perform functional and timing simulations, you must use the altera_mf.v library located in the <Quartus II installation directory>\eda\sim_lib directory.

For VHDL, you must use the altera_mf.vhd library located in the <Quartus II installation directory>\eda\sim_lib directory.

The VHDL component declaration file is located in the altera_mf_components.vhd library in the <Quartus II installation directory>\eda\sim_lib directory"

So also there, according to the manual, reference to sim_lib seems mandatory for simulation and modelsim and Q17.1 (on my system) do not refer to the right directory by default.

So my problem how to change the directory altera_mf referes to on my system to enable me to simulate ALTFP_LOG remains on the table.

Best Regards,

Johi.

There is a simple answer to this. Remove the sclr port from your code. It is clearly not required.​ What you haven't shown is your code where you instantiate the squarer component.

Hello Tricky,

My point is maybe not clear:

It is not my code but the altera ip code for ALT_LOG that instantiates altsquare.

I only instantiate ALT_LOG.

I know you can help me sort this out, my post above explains in detail what te problem is. I think i need to do what is the case below, but i do not know how.

https://www.intel.com/content/www/us/en/programmable/quartushelp/13.1/mergedProjects/hdl/mega/mega_file_altsquare.htm

Best Regards,

Johi.

Dear All,

Please find an archive of the demo project I used to illustrate my issue.

Best Regards,

Johi.