Forum Discussion
Okay, I managed to resolve your issue. The instance of the FloatLn function has in its component declaration the sclr port, where as in the component port map the said 'sclr' port is missing and in the VHDL source also the port is not there.
You just need to comment out the sclr port in the FloatLn.vhd file as shown below:
COMPONENT altsquare
GENERIC
(
DATA_WIDTH : NATURAL;
PIPELINE : NATURAL;
REPRESENTATION : STRING := "UNSIGNED";
RESULT_ALIGNMENT : STRING := "LSB";
RESULT_WIDTH : NATURAL;
lpm_type : STRING := "altsquare"
);
PORT
(
aclr : IN STD_LOGIC := '0';
clock : IN STD_LOGIC := '1';
data : IN STD_LOGIC_VECTOR(DATA_WIDTH-1 DOWNTO 0);
ena : IN STD_LOGIC := '1';
result : OUT STD_LOGIC_VECTOR(RESULT_WIDTH-1 DOWNTO 0)
--sclr : IN STD_LOGIC := '0'
);
end component;
squarer : altsquare
GENERIC MAP (
DATA_WIDTH => 13,
PIPELINE => 1,
REPRESENTATION => "UNSIGNED",
RESULT_ALIGNMENT => "MSB",
RESULT_WIDTH => 14
)
PORT MAP ( -- No sclr port here
aclr => aclr,
clock => clock,
data => squarerIn,
ena => clk_en,
result => wire_squarer_result
);
Recompile all the files/design after making this edit. Then simulate it.
I guess this issue may need to be fixed by Intel(Altera).