Contributor
Frequent ContributorOkay, let me clear things up a bit.
#1. MentorGraphics who is the developer of ModelSim does not and will not include any EDA vendor like Intel(Altera)/Xilinx FPGA libraries by default in their ModelSim or QuestaSim products. They only include standard IEEE VHDL & Verilog libraries.
#2. The version of ModelSim that is shipped along with Quartus has been customized by Intel (Altera) by adding their respective pre-compiled FPGA and device libraries that are needed for simulation. These are provided so that users need not compile the entire FPGA and device libraries again.
#3. The Quartus tools come with two versions of the libraries. One that is located in the eda/sim_libs is meant only for Simulation purposes. While the other library is meant for synthesis.
Do not use the synthesis library for simulation purposes. Use only the simulation libraries for RTL simulations.
Modules that are present in the sim libraries and the synthesis libraries are different in terms of ports as well as timing and other information. Simulation libraries may contain the basic functional interfaces that are needed for simulation , where as the synthesis libraries will contain all of the port information for that IP/block. This will also include interfaces/ports that you are not using in the design.
#4. When creating designs which use IPs or Megafunctions, you have to generate the simulation model for the IP or megafunction that you are using. This will generate the required simulation models for the IPs/blocks used and you can compile them along with the rest of the RTL for functional simulation.
#5. When you create a variation of a Megafunction/IP block, always create the simulation models as well as the instantiation templates. This way the tool will create a template that is customized as per your requirements.
Please do not edit the simulation or synthesis models located in the quartus folders as it would lead to errors when generating the same IP blocks later. As stated above, always generate a simulation model for the IPs that you're using and compile them along with your design. Quartus will also generate a script that you can use to compile your design.
