Forum Discussion
Abe
Frequent Contributor
7 years agoAre you trying to do a post synthesis simulation or RTL simulation? If you're doing a RTL simulation you need to include the altera_mf and any other altera library in the VHDL code.
library altera_mf;
Use altera_mf.all;
You could try using the above statements in the VHDL code. Open the altera_mf library source code and see under which component is the module in question. include that in the "USE altera_mf.<component_name>.all;
If this doesn't work, then what you can try is to compile the altera_mf VHDL sources/library into your work library. This will include all of the required modules and your design will compile & simulate.
If you're doing a post-synthesis simulation the libraries will get used by default.