Altera_Forum
Honored Contributor
14 years agoHow can i optimize the interconnect between BRAM and logic element
Hi, all
I have build a NiosII processor with SOPC tool and find that the utilization of BRAM is not efficient. My target device is EC3C25 and its BRAM has 608256Bits, But I can use about 53%. If I want to increase the cache size of NiosII processor, QuartusII can not fit well and give error which show that project need more than 66 BRAM to fit. I think the root cause is the lack of interconnect resourse. Now the problem in front of me is that how can i optimize the interconnect and let me take good use of BRAM and result in good SOPC system performance. Good guide is appreciated! Thank you for you help!