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Altera_Forum's avatar
Altera_Forum
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14 years ago

How can i optimize the interconnect between BRAM and logic element

Hi, all I have build a NiosII processor with SOPC tool and find that the utilization of BRAM is not efficient. My target device is EC3C25 and its BRAM has 608256Bits, But I can use about 53%. ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

the problem has to do with how Quartus fits block RAM for performance reasons, it doesn't seem to want to mux the output of the RAM blocks

my advice is to decrease the size of the on-chip RAM until it fits or else write your own optimized HDL RAM which will include output muxes and maybe pipelines. then import the HDL as a custom component