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Altera_Forum's avatar
Altera_Forum
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13 years ago

How can I know what compiled libraries needed for my design simulation?

I make design in Quartus II. Then I need simulate it in Modelsim. I don't want to use the Quartus nativelink to run Modelsim for simulation. I prefer to do is creating the simulation project, add the design files into project and do simulation.

However, there is a problem that I need to add needed compiled libraries before I can do simulation (as attachment showed). In normal case, the design needs multiple libraries.So how can I know what compiled libraries I need for simulation? Or is there any other approach that I don't need to add the libraries one by one manually?

Thanks a lot.

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  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    --- Quote Start ---

    you should only need to map those libraries once. It should place them in the modelsim.ini file

    --- Quote End ---

    Thanks, so that means everytime I run modelsim, then these libraries will be automatically mapped to my working library. I will try to use command, if I have questions, I will post here.

    Thanks.
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    I found it seems I described my question not clear. What I really want to ask is: when I simulate a design, how can I know what resource libraries needed to link? The resource libraries are libraries from Altera and I compiled them in Modelsim. I need to link the needed resource libraries when I simulate my designs.

    Thanks very much.
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    you dont need to know, as long as they are mapped in modelsim, you can access them from VHDL.

  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    --- Quote Start ---

    you dont need to know, as long as they are mapped in modelsim, you can access them from VHDL.

    --- Quote End ---

    Thanks, Tricky. What do you mean I can acess them from VHDL? When I programed, they are listed in my VHDL code?

    And how about if I program using Verilog?
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    Using VHDL, you map libraries directly: 

    
library some_library;
use some_library.some_package.all;
....
  --direct instantiation
  some_inst : entity my_library.some_entity(ent_arch)
  generic map ()
  port map ();
 --etc

    So as long as you have the libraries mapped in modelsim, you write code like the above to access them. If they are not mapped, you'll get and error when you compile.

    Verilog has no idea of libraries, so it will primarily search the work library for a design unit. YOu can add libraries to the search with the -L option on vsim:

    vsim some_entity -L library1 -L library2 etc
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    --- Quote Start ---

    Using VHDL, you map libraries directly: 

    
library some_library;
use some_library.some_package.all;
....
  --direct instantiation
  some_inst : entity my_library.some_entity(ent_arch)
  generic map ()
  port map ();
 --etc

    So as long as you have the libraries mapped in modelsim, you write code like the above to access them. If they are not mapped, you'll get and error when you compile.

    Verilog has no idea of libraries, so it will primarily search the work library for a design unit. YOu can add libraries to the search with the -L option on vsim:

    vsim some_entity -L library1 -L library2 etc

    --- Quote End ---

    "vsim some_entity -L library1 -L library2"， this is what I want to ask. I have to add these libraries otherwise I can't simulate. However, for a specific design, how can I know what libraries I need? E.g. I make a design in a cyclone IV chip with some IPs: FIFO, PLL. I know I need cycloneiv_ver, and what libraries need for IPs like FIFO, PLL? How can I know that?

    Now the approach I take is: I run the simulate through nativelink, and check the generated .do file to read the command. Anyother better approach?

    And for VHDL design, do I need to add libraries with command:

    vsim library1 library2 ……

    Thanks.
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    you only need the -L for verilog code as verilog has no knowledge of libraries, so the -L tells it where to search for modules. For VHDL you dont need any -L arguments because you already mapped them in the code.

    Generally you only use the altera_mf library, as that is where most of the IP lives. That library will call in items from cyclone IV or wherever depending on the generics on the blocks. But if you are missing something, it will tell you (and in VHDL it will tell you which library it cannot find). The only way to really know what libraries you need is by looking at the code.

    I have never used nativelink, or a generated .do file, I always do simulations manually.
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    You mentioned that "Generally you only use the altera_mf library, as that is where most of the IP lives." So if my design want to use some common IPs, I need to map the altera_mf library at the beginning of my VHDL code as:

    library altera_mf

    Right? All the libraries I need to use I need map at the beginning of the VHDL codes, right?

    Thanks.