How can I know what compiled libraries needed for my design simulation?

Using VHDL, you map libraries directly:

library some_library;
use some_library.some_package.all;
....
  --direct instantiation
  some_inst : entity my_library.some_entity(ent_arch)
  generic map ()
  port map ();
 --etc

So as long as you have the libraries mapped in modelsim, you write code like the above to access them. If they are not mapped, you'll get and error when you compile.

Verilog has no idea of libraries, so it will primarily search the work library for a design unit. YOu can add libraries to the search with the -L option on vsim:

vsim some_entity -L library1 -L library2 etc