I make design in Quartus II. Then I need simulate it in Modelsim. I don't want to use the Quartus nativelink to run Modelsim for simulation. I prefer to do is creating the simulation project, add the design files into project and do simulation. However, there is a problem that I need to add needed compiled libraries before I can do simulation (as attachment showed). In normal case, the design needs multiple libraries.So how can I know what compiled libraries I need for simulation? Or is there any other approach that I don't need to add the libraries one by one manually? Thanks a lot.

If you install Modelsim Altera or Starter edition, it comes with all the libraries pre-compiled for you. Either map to them manually, or copy and paste then entries out of the modelsim.ini file into your other version of modelsim's ini file.

--- Quote Start --- If you install Modelsim Altera or Starter edition, it comes with all the libraries pre-compiled for you. Either map to them manually, or copy and paste then entries out of the modelsim.ini file into your other version of modelsim's ini file. --- Quote End --- Hi Tricky, thanks very much for your answer. But it seems you misunderstood my question. I already compiled libraries and map them to Modelsim. My question is when I want to simulate a design in Modelsim, I create a project and create a simulation configuration file as the attached image, in this interface, it asks me to add libraries, how can I know which libraries I needed to add, for my design simulation?

Are you talking about HDL simulation or post place and route simulation? FOr HDL sim you just compile all the files with vcom(vhdl) or vlog(verilog) and then vsim the component (the testbench) you want to simulate. libraries can be setup with vlib and Vmap. Modelsim project files are a waste of time.

--- Quote Start --- Are you talking about HDL simulation or post place and route simulation? FOr HDL sim you just compile all the files with vcom(vhdl) or vlog(verilog) and then vsim the component (the testbench) you want to simulate. libraries can be setup with vlib and Vmap. Modelsim project files are a waste of time. --- Quote End --- Thanks, Tricky. So I think you suggested me to use tcl command instead of using GUI. Let me make my question more clear. I need to do simulation in both HDL level and Post PR level. In most cases, my designs adopts many soft IP cores (PCIe, FIR, Coding and decoding). My designs also adopts some hard IP cores (Gigbit transceivers). And my designs will be in a series device, e.g, Starix V. If I want to simulate in HDL levels, based on my understanding I need assign libraries, which Modelsim needed, for simulation. If I want to simulate in Post PR level, I also need to assign libraries in Modelsim, but these libraries may be different from which needed in HDL simulation. This is my understanding, it may be wrong? So now my question is: there are so many compiled libraries in Modelsim, how can I know which are needed for my designs? Does this must be done by manually? Or there is a better approach, that can be done automatically?

BTW, I want to learn how to use script to do simulation in Modelsim. Is there some good example script which do some simple operation I can learn? Thanks very much.

How can I know what compiled libraries needed for my design simulation?

20 Replies

Altera_Forum
Honored Contributor
13 years ago
If you install Modelsim Altera or Starter edition, it comes with all the libraries pre-compiled for you. Either map to them manually, or copy and paste then entries out of the modelsim.ini file into your other version of modelsim's ini file.
Altera_Forum
Honored Contributor
13 years ago
--- Quote Start ---
If you install Modelsim Altera or Starter edition, it comes with all the libraries pre-compiled for you. Either map to them manually, or copy and paste then entries out of the modelsim.ini file into your other version of modelsim's ini file.
--- Quote End ---

Hi Tricky, thanks very much for your answer. But it seems you misunderstood my question. I already compiled libraries and map them to Modelsim.

My question is when I want to simulate a design in Modelsim, I create a project and create a simulation configuration file as the attached image, in this interface, it asks me to add libraries, how can I know which libraries I needed to add, for my design simulation?
Altera_Forum
Honored Contributor
13 years ago
Are you talking about HDL simulation or post place and route simulation?

FOr HDL sim you just compile all the files with vcom(vhdl) or vlog(verilog) and then vsim the component (the testbench) you want to simulate. libraries can be setup with vlib and Vmap. Modelsim project files are a waste of time.
Altera_Forum
Honored Contributor
13 years ago
--- Quote Start ---
Are you talking about HDL simulation or post place and route simulation?

FOr HDL sim you just compile all the files with vcom(vhdl) or vlog(verilog) and then vsim the component (the testbench) you want to simulate. libraries can be setup with vlib and Vmap. Modelsim project files are a waste of time.
--- Quote End ---

Thanks, Tricky. So I think you suggested me to use tcl command instead of using GUI. Let me make my question more clear. I need to do simulation in both HDL level and Post PR level.

In most cases, my designs adopts many soft IP cores (PCIe, FIR, Coding and decoding). My designs also adopts some hard IP cores (Gigbit transceivers). And my designs will be in a series device, e.g, Starix V.

If I want to simulate in HDL levels, based on my understanding I need assign libraries, which Modelsim needed, for simulation. If I want to simulate in Post PR level, I also need to assign libraries in Modelsim, but these libraries may be different from which needed in HDL simulation. This is my understanding, it may be wrong?

So now my question is: there are so many compiled libraries in Modelsim, how can I know which are needed for my designs? Does this must be done by manually? Or there is a better approach, that can be done automatically?
Altera_Forum
Honored Contributor
13 years ago
BTW, I want to learn how to use script to do simulation in Modelsim. Is there some good example script which do some simple operation I can learn?

Thanks very much.

Altera_Forum

Honored Contributor

13 years ago

the easiest thing to do is just map all of the altera libraries in your modelsim.ini file, then all libraries are available to all compilations all the time. but here is a quick tcl file that should set them all up from wherever you are.


set LibPath C:/altera/modelsim/modelsim_ae/altera
          
vlib altera_mf         
vlib altera            
vlib lpm               
vlib 220model            
vlib max               
vlib maxii             
vlib stratix           
vlib stratixii         
vlib stratixiii        
vlib stratixiv
vlib stratixv      
vlib cyclone           
vlib cycloneii         
vlib cycloneiii        
vlib sgate             
vlib stratixgx         
vlib altgxb            
vlib stratixgx_gxb     
vlib altera_mf_ver     
vlib lpm_ver           
vlib 220model_ver      
vlib alt_ver          
vlib max_ver           
vlib maxii_ver         
vlib stratix_ver       
vlib stratixii_ver     
vlib stratixiii_ver    
vlib stratixiv_ver
vlib stratixv_ver
vlib cyclone_ver       
vlib cycloneii_ver     
vlib cycloneiii_ver    
vlib sgate_ver         
vlib stratixgx_ver     
vlib altgxb_ver        
vlib stratixgx_gxb_ver 
vmap altera_mf         $LibPath/vhdl/altera_mf
vmap altera            $LibPath/vhdl/altera
vmap lpm               $LibPath/vhdl/220model
vmap 220model          $LibPath/vhdl/220model
vmap max               $LibPath/vhdl/max
vmap maxii             $LibPath/vhdl/maxii
vmap stratix           $LibPath/vhdl/stratix
vmap stratixii         $LibPath/vhdl/stratixii
vmap stratixiii        $LibPath/vhdl/stratixiii
vmap stratixiv         $LibPath/vhdl/stratixiv
vmap stratixv          $LibPath/vhdl/stratixv
vmap cyclone           $LibPath/vhdl/cyclone
vmap cycloneii         $LibPath/vhdl/cycloneii
vmap cycloneiii        $LibPath/vhdl/cycloneiii
vmap sgate             $LibPath/vhdl/sgate
vmap stratixgx         $LibPath/vhdl/stratixgx
vmap altgxb            $LibPath/vhdl/altgxb
vmap stratixgx_gxb     $LibPath/vhdl/stratixgx_gxb
vmap altera_mf_ver     $LibPath/verilog/altera_mf
vmap altera_ver        $LibPath/verilog/altera
vmap lpm_ver           $LibPath/verilog/220model
vmap 220model_ver      $LibPath/verilog/220model
vmap max_ver           $LibPath/verilog/max
vmap maxii_ver         $LibPath/verilog/maxii
vmap stratix_ver       $LibPath/verilog/stratix
vmap stratixii_ver     $LibPath/verilog/stratixii
vmap stratixiii_ver    $LibPath/verilog/stratixiii
vmap stratixiv_ver     $LibPath/verilog/stratixiv
vmap stratixv_ver      $LibPath/verilog/stratixv
vmap cyclone_ver       $LibPath/verilog/cyclone
vmap cycloneii_ver     $LibPath/verilog/cycloneii
vmap cycloneiii_ver    $LibPath/verilog/cycloneiii
vmap sgate_ver         $LibPath/verilog/sgate
vmap stratixgx_ver     $LibPath/verilog/stratixgx
vmap altgxb_ver        $LibPath/verilog/altgxb
vmap stratixgx_gxb_ver $LibPath/verilog/stratixgx_gxb

Altera_Forum
Honored Contributor
13 years ago
The key commands you need are:

vcom/vlog <somefile> -- VHDL/Verilog compile command. Will by default compile into the work library, but using the -work option you can chose what library to compile into
vsim <my_design_unit> -- starts the simulation of the design
run X ns -- run simulation for X ns (-all option just runs forever until testbench stops)
vlib <some_library> -- creates a library
vmap <some_library> <libary_directory> -- maps a libaray to the specified directory
do <somefile> -- runs a tcl script

Thats about all the commands I use. I use the gui for adding waves to a wave window then save it to some .do file that I can then just run later.
Altera_Forum
Honored Contributor
13 years ago
oh, I forgot -

restart - restarts a simulation.

you can run vcom/vlog during a simulation, and it will reload the recompiled design after a restart, so you dont have to restart the entire sim via vsim.

Altera_Forum

Honored Contributor

13 years ago

--- Quote Start ---


set LibPath C:/altera/modelsim/modelsim_ae/altera
          
vlib altera_mf         
vlib altera            
vlib lpm               
vlib 220model            
vlib max               
vlib maxii             
vlib stratix           
vlib stratixii         
vlib stratixiii        
vlib stratixiv
vlib stratixv      
vlib cyclone           
vlib cycloneii         
vlib cycloneiii        
vlib sgate             
vlib stratixgx         
vlib altgxb            
vlib stratixgx_gxb     
vlib altera_mf_ver     
vlib lpm_ver           
vlib 220model_ver      
vlib alt_ver          
vlib max_ver           
vlib maxii_ver         
vlib stratix_ver       
vlib stratixii_ver     
vlib stratixiii_ver    
vlib stratixiv_ver
vlib stratixv_ver
vlib cyclone_ver       
vlib cycloneii_ver     
vlib cycloneiii_ver    
vlib sgate_ver         
vlib stratixgx_ver     
vlib altgxb_ver        
vlib stratixgx_gxb_ver 
vmap altera_mf         $LibPath/vhdl/altera_mf
vmap altera            $LibPath/vhdl/altera
vmap lpm               $LibPath/vhdl/220model
vmap 220model          $LibPath/vhdl/220model
vmap max               $LibPath/vhdl/max
vmap maxii             $LibPath/vhdl/maxii
vmap stratix           $LibPath/vhdl/stratix
vmap stratixii         $LibPath/vhdl/stratixii
vmap stratixiii        $LibPath/vhdl/stratixiii
vmap stratixiv         $LibPath/vhdl/stratixiv
vmap stratixv          $LibPath/vhdl/stratixv
vmap cyclone           $LibPath/vhdl/cyclone
vmap cycloneii         $LibPath/vhdl/cycloneii
vmap cycloneiii        $LibPath/vhdl/cycloneiii
vmap sgate             $LibPath/vhdl/sgate
vmap stratixgx         $LibPath/vhdl/stratixgx
vmap altgxb            $LibPath/vhdl/altgxb
vmap stratixgx_gxb     $LibPath/vhdl/stratixgx_gxb
vmap altera_mf_ver     $LibPath/verilog/altera_mf
vmap altera_ver        $LibPath/verilog/altera
vmap lpm_ver           $LibPath/verilog/220model
vmap 220model_ver      $LibPath/verilog/220model
vmap max_ver           $LibPath/verilog/max
vmap maxii_ver         $LibPath/verilog/maxii
vmap stratix_ver       $LibPath/verilog/stratix
vmap stratixii_ver     $LibPath/verilog/stratixii
vmap stratixiii_ver    $LibPath/verilog/stratixiii
vmap stratixiv_ver     $LibPath/verilog/stratixiv
vmap stratixv_ver      $LibPath/verilog/stratixv
vmap cyclone_ver       $LibPath/verilog/cyclone
vmap cycloneii_ver     $LibPath/verilog/cycloneii
vmap cycloneiii_ver    $LibPath/verilog/cycloneiii
vmap sgate_ver         $LibPath/verilog/sgate
vmap stratixgx_ver     $LibPath/verilog/stratixgx
vmap altgxb_ver        $LibPath/verilog/altgxb
vmap stratixgx_gxb_ver $LibPath/verilog/stratixgx_gxb

--- Quote End ---

Thanks very much. So I can write all of these commands in my .do file. And execute it before I do simulation, right?

Altera_Forum
Honored Contributor
13 years ago
you should only need to map those libraries once. It should place them in the modelsim.ini file

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How can I know what compiled libraries needed for my design simulation?

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