How can I know what compiled libraries needed for my design simulation?

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the easiest thing to do is just map all of the altera libraries in your modelsim.ini file, then all libraries are available to all compilations all the time. but here is a quick tcl file that should set them all up from wherever you are.

set LibPath C:/altera/modelsim/modelsim_ae/altera
          
vlib altera_mf         
vlib altera            
vlib lpm               
vlib 220model            
vlib max               
vlib maxii             
vlib stratix           
vlib stratixii         
vlib stratixiii        
vlib stratixiv
vlib stratixv      
vlib cyclone           
vlib cycloneii         
vlib cycloneiii        
vlib sgate             
vlib stratixgx         
vlib altgxb            
vlib stratixgx_gxb     
vlib altera_mf_ver     
vlib lpm_ver           
vlib 220model_ver      
vlib alt_ver          
vlib max_ver           
vlib maxii_ver         
vlib stratix_ver       
vlib stratixii_ver     
vlib stratixiii_ver    
vlib stratixiv_ver
vlib stratixv_ver
vlib cyclone_ver       
vlib cycloneii_ver     
vlib cycloneiii_ver    
vlib sgate_ver         
vlib stratixgx_ver     
vlib altgxb_ver        
vlib stratixgx_gxb_ver 
vmap altera_mf         $LibPath/vhdl/altera_mf
vmap altera            $LibPath/vhdl/altera
vmap lpm               $LibPath/vhdl/220model
vmap 220model          $LibPath/vhdl/220model
vmap max               $LibPath/vhdl/max
vmap maxii             $LibPath/vhdl/maxii
vmap stratix           $LibPath/vhdl/stratix
vmap stratixii         $LibPath/vhdl/stratixii
vmap stratixiii        $LibPath/vhdl/stratixiii
vmap stratixiv         $LibPath/vhdl/stratixiv
vmap stratixv          $LibPath/vhdl/stratixv
vmap cyclone           $LibPath/vhdl/cyclone
vmap cycloneii         $LibPath/vhdl/cycloneii
vmap cycloneiii        $LibPath/vhdl/cycloneiii
vmap sgate             $LibPath/vhdl/sgate
vmap stratixgx         $LibPath/vhdl/stratixgx
vmap altgxb            $LibPath/vhdl/altgxb
vmap stratixgx_gxb     $LibPath/vhdl/stratixgx_gxb
vmap altera_mf_ver     $LibPath/verilog/altera_mf
vmap altera_ver        $LibPath/verilog/altera
vmap lpm_ver           $LibPath/verilog/220model
vmap 220model_ver      $LibPath/verilog/220model
vmap max_ver           $LibPath/verilog/max
vmap maxii_ver         $LibPath/verilog/maxii
vmap stratix_ver       $LibPath/verilog/stratix
vmap stratixii_ver     $LibPath/verilog/stratixii
vmap stratixiii_ver    $LibPath/verilog/stratixiii
vmap stratixiv_ver     $LibPath/verilog/stratixiv
vmap stratixv_ver      $LibPath/verilog/stratixv
vmap cyclone_ver       $LibPath/verilog/cyclone
vmap cycloneii_ver     $LibPath/verilog/cycloneii
vmap cycloneiii_ver    $LibPath/verilog/cycloneiii
vmap sgate_ver         $LibPath/verilog/sgate
vmap stratixgx_ver     $LibPath/verilog/stratixgx
vmap altgxb_ver        $LibPath/verilog/altgxb
vmap stratixgx_gxb_ver $LibPath/verilog/stratixgx_gxb

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Thanks very much. So I can write all of these commands in my .do file. And execute it before I do simulation, right?