Forum Discussion
Altera_Forum
Honored Contributor
13 years agoAre you talking about HDL simulation or post place and route simulation?
FOr HDL sim you just compile all the files with vcom(vhdl) or vlog(verilog) and then vsim the component (the testbench) you want to simulate. libraries can be setup with vlib and Vmap. Modelsim project files are a waste of time.