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Altera_Forum's avatar
Altera_Forum
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11 years ago

How can I connect multiple logic wires to module outputs?

I have a System Verilog syntax related question. In my Quartus II project (for Cyclone IV) I need to have two modules control the SRAM ports (SRAM_DQ, SRAM_OE_N, SRAM_WE_N, etc.). These two modules (one is the NIOS SOC module and another is the VGA color mapping module) access and modify the SRAM port outputs. When directly connecting the inputs and outputs of these modules to the SRAM pins in my top-level file, Quartus gives me errors that these pins can't be assigned more than one value.

One solution I tried was to create "logic" wires in the top-level file and adding statements like

assign SRAM_OE_N = sramOE_N; // SRAM_OE_N is the output pin to SRAM, sramOE_N is a local "logic" wire

and connecting these logic wires instead to the individual modules but this didn't work either. How can I solve this?

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    Quartus has told you exactly what is wrong... "pins can't be assigned to more than one value".

    Say the Nios SoC wants to access the SRAM and tries to drive one of the pins, say, low. But at the same time the VGA controller wants to access the SRAM and drive the same pin high. What value should the pin be?

    You need some form of Arbitration logic to decide who has access to the memory and when.
  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    Do you have any suggestions on what methods work well to solve this kind of a problem? I think one solution is to create another "sram_controller" module which will take as inputs the NIOS SoC connections and the VGA controller inputs and then based on which state the system is in, wire the corresponding inputs to the outputs. But is there a better solution?

  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    If you have multiple devices trying to connect to the same destination, you build what it called an arbiter. It will select which device should have access. There are several arbitration schemes that can be used (eg. highest/lowest has priorty, round robin). There should be an arbiter IP block in the Qsys library.