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Altera_Forum's avatar
Altera_Forum
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10 years ago

How can I connect multiple logic wires to module outputs?

I have a System Verilog syntax related question. In my Quartus II project (for Cyclone IV) I need to have two modules control the SRAM ports (SRAM_DQ, SRAM_OE_N, SRAM_WE_N, etc.). These two modules (...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

If you have multiple devices trying to connect to the same destination, you build what it called an arbiter. It will select which device should have access. There are several arbitration schemes that can be used (eg. highest/lowest has priorty, round robin). There should be an arbiter IP block in the Qsys library.