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Honored Contributor
Honored ContributorHow can I connect multiple logic wires to module outputs?
I have a System Verilog syntax related question. In my Quartus II project (for Cyclone IV) I need to have two modules control the SRAM ports (SRAM_DQ, SRAM_OE_N, SRAM_WE_N, etc.). These two modules (...
Altera_ForumHonored Contributor
Honored ContributorDo you have any suggestions on what methods work well to solve this kind of a problem? I think one solution is to create another "sram_controller" module which will take as inputs the NIOS SoC connections and the VGA controller inputs and then based on which state the system is in, wire the corresponding inputs to the outputs. But is there a better solution?
